ANALYSIS AND CHARACTERIZATION OF BICMOS FOR HIGH-SPEED DIGITAL LOGIC

被引：36

作者：

GREENEICH, EW ^{[1
]}

MCLAUGHLIN, KL ^{[1
]}

机构：

[1] MOTOROLA INC,TECH STAFF,MESA,AZ 85202

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1988年 / 23卷 / 02期

关键词：

INTEGRATED CIRCUITS; DIGITAL - LOGIC DESIGN - SEMICONDUCTOR DEVICES; BIPOLAR - Mathematical Models;

D O I：

10.1109/4.1022

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A combined bipolar and CMOS (BiCMOS) logic gate, capable of driving large capacitive loads at high speed, is analyzed and characterized. A simple analytical model which accurately predicts the transient response of the BiCMOS gate is described. At moderate and large loads, saturation of the bipolar transistors due to collector resistance can dominate the transient response. Device scaling issues are discussed for minimizing gate delay at various loading conditions.

引用

页码：558 / 565

页数：8

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[2]

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KURITA, K ;

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[8]

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