A 10-NS 54 X 54-B PARALLEL STRUCTURED FULL ARRAY MULTIPLIER WITH 0.5-MU-M CMOS TECHNOLOGY

被引:64
作者
MORI, J
NAGAMATSU, M
HIRANO, M
TANAKA, S
NODA, M
TOYOSHIMA, Y
HASHIMOTO, K
HAYASHIDA, H
MAEGUCHI, K
机构
[1] TOSHIBA CO LTD,SEMICOND DEVICE ENGN LAB,LOG DEVICE DESIGN SECT,KAWASAKI 210,JAPAN
[2] TOSHIBA CO LTD,SEMICOND DEVICE ENGN LAB,DEPT ADV LOG MEMORY TECHNOL,KAWASAKI 210,JAPAN
关键词
5;
D O I
10.1109/4.75061
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper describes a 54 x 54-b multiplier fabricated by double-metal 0.5-mu-m CMOS technology. The 54 x 54-b full array has been adopted to complete multiplication within one latency. A 10-ns multiplication time has been achieved by optimizing both the propagation time of the part consisting of 4-2 compressors [1] and the propagation time of the final adder part. The n-channel pass-transistor circuit and the p-channel load circuit have been employed at the critical blocks to improve the multiplication speed. This multiplier is intended to be applied to double-precision floating-point data processing based on the IEEE standard up to a clock range of 100 MHz.
引用
收藏
页码:600 / 606
页数:7
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