MONOLITHIC MATCHING OF SILICON DETECTORS WITH HIGH NUMBER OF CHANNELS AT VERY SHORT SHAPING TIME

The HF2CMOS bipolar-CMOS monolithic technology enables the realization of very fast charge sensitive preamplifiers (with bipolar npn input devices) needed in experiments with very large numbers of channels and high rates of incoming events, like those to be performed at the future SSC/LHC hadron colliders. Two preamplifier versions have been realized, V1 and V2. Both display about 100 MHz small signal bandwidth, their power dissipation can vary between 6 and 45 mW, as a function of dynamic requirements, and can be optimized by programming the current consumption and supply voltage. Their slew rate is 700 and 250 V/-mu-s for versions V1 and V2, respectively. The base spreading resistance of version V2 was reduced to 14-OMEGA, as compared with 370-OMEGA of version V1. The equivalent noise charge, for version V2, is about 4700 e(RMS) at 20 ns RC-CR shaping time, for 150 pF detector capacitance. An appropriate detector matching approach allows modularity in the integration, with an on chip implementation of an RC-CR shaper. Version V1 of the preamplifier in this configuration, on printed boards, has been successfully tested.