A SELF-ALIGNED ELEVATED SOURCE DRAIN MOSFET

An advanced elevated source / drain CMOS process which features self-aligned LDD and channel implantation is described. This process employs a single selective silicon deposition step to define both the epitaxial source / drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source / drain CMOS processes, the final MOSFET structure provides self-alignment of the lightly doped LDD regions with the heavily doped channel regions. Excellent short-channel device characteristics have been obtained. © 1990 IEEE