MEASUREMENT OF THE LOCAL LATCH-UP SENSITIVITY BY MEANS OF COMPUTER-CONTROLLED SCANNING ELECTRON-MICROSCOPY

A scanning electron microscopy (SEM) technique for the study of the local sensitivity to latch-up of CMOS integrated circuits is discussed. The technique is independent of a particular electric firing mechanism of latchup and does not require in-depth electrical characterization of the IC before the analysis. The electron beam in the SEM is adopted as a localized current injector, and the injected carriers are used to induce the latch-up state rather than to visualize its paths. A minicomputer-based system drives the beam position and automatically blanks the beam if the scan path has to cross areas which should be protected from charge injection. An example of application is described.