10K-GATE GAAS JFET SEA OF GATES

被引：3

作者：

KAWASAKI, H

WADA, M

HIDA, Y

TAKANO, C

KASAHARA, J

机构：

[1] Sony Corporation Research Center, Hodogaya-ku, Yokohama 240

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1991年 / 26卷 / 10期

关键词：

D O I：

10.1109/4.90087

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The first GaAs 10K-gate sea of gates has been successfully fabricated using JFET's with a gate length of 0.5-mu-m. A basic cell is designed to constitute both a DCFL four-NOR circuit and an SCFL inverter circuit with an identical enhancement-type JFET. Each input and output level is designed to be compatible with Si ECL, CMOS, and TTL logic levels. Unloaded and loaded DCFL gate delays are 21 and 180 ps/gate with power consumption of 0.4 and 0.5 mW/gate, respectively. The toggle frequency of the T-type flip-flop is obtained to be 3.9 and 4.4 GHz for DCFL and SCFL, respectively.

引用

页码：1367 / 1370

页数：4

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[5]

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