A 40-PS HIGH ELECTRON-MOBILITY TRANSISTOR 4.1-K GATE ARRAY

被引：18

作者：

KAJII, K

WATANABE, Y

SUZUKI, M

HANYU, I

KOSUGI, M

ODANI, K

MIMURA, T

ABE, M

机构：

[1] Fujitsu Ltd, Atsugi, Jpn, Fujitsu Ltd, Atsugi, Jpn

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1988年 / 23卷 / 02期

关键词：

INTEGRATED CIRCUITS; VLSI - Fabrication - LOGIC DESIGN;

D O I：

10.1109/4.1011

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A high-electron mobility transistor (HEMT) 4. 1K-gate array has been developed, using a selective dry etching process and a MBE (molecular-beam epitaxy) growth technology. The circuit design uses direct-coupled FET logic (DCFL). The chip contains 4096 NOR gates, each with a 0. 8- mu m gate length, and measures 6. 3 mm multiplied by 4. 8 mm. A basic gate delay of 40 ps has been achieved. A 16 multiplied by 16-bit parallel multiplier, used to test this array, has a multiplication time of 4. 1 ns at 300 K, where the power dissipation is 6. 2 W.

引用

页码：485 / 489

页数：5

共 12 条

[1]

Abe M., 1983, GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuit Symposium. Technical Digest 1983, P158

[2] A FULLY OPERATIONAL 1-KBIT HEMT STATIC RAM [J].