MERGED BICMOS LOGIC TO EXTEND THE CMOS BICMOS PERFORMANCE CROSSOVER BELOW 2.5-V SUPPLY

This paper will discuss the merged BiCMOS (MBiCMOS) gate, a unique circuit configuration to improve BiCMOS gate performance at low supply voltages. Measured results from both a 2-mu-m process with triple-diffused n-p-n bipolar transistors and a 1-mu-m conventional buried-layer/epi process with 15-GHz n-p-n bipolar devices indicate that MBiCMOS provides measured delay advantages over CMOS to below 2.5-V supplies, in a compact four-device cell that does not require any change in the standard BiCMOS processing sequence or any more power than a standard BiCMOS gate. Gates designed for fabrication in a 0.5-mu-m technology and simulated using measured device parameters show MBiCMOS/CMOS performance crossover voltages of 2.19 V, as compared to a crossover of 2.63 V for standard BiCMOS/CMOS. Use of a modified MBiCMOS gate extends the performance crossover to 1.9 V with the addition of a single implant to implement zero-threshold PMOS devices. With modified MBiCMOS, the useful operating range for BiCMOS technology is extended to the submicrometer sub-2-V regime. A full-swing version of the MBiCMOS gate (FS-MBiCMOS) is introduced. Simulations of 2-mu-m gates show FS-MBiCMOS/CMOS performance crossover voltages of 2.2 V.