EXPERIMENTAL EVALUATION OF SOME RAPID SINGLE FLUX QUANTUM CELLS

We have studied some basic cells in the Rapid Single Flux Quantum family of superconductive logic circuits. An input stage, a buffer, and an OR gate were simulated and laid out for a standard niobium-based fabrication process. The resulting circuits perform properly for clock speeds up to 1 GHz-the highest speed used in this work. For the simpler circuits tested, the measured margins are wide, consistent with simulations, and not very dependent on clock speed. However, margin decreases with increased circuit complexity.