REDUNDANCY IDENTIFICATION REMOVAL AND TEST-GENERATION FOR SEQUENTIAL-CIRCUITS USING IMPLICIT STATE ENUMERATION

被引：39

作者：

CHO, H ^{[1
]}

HACHTEL, GD ^{[1
]}

SOMENZI, F ^{[1
]}

机构：

[1] UNIV COLORADO,DEPT ELECT & COMP ENGN,BOULDER,CO 80303

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1993年 / 12卷 / 07期

关键词：

D O I：

10.1109/43.238030

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The recent advances in finite state machine (FSM) verification based on implicit state enumeration provide a powerful method for FSM verification. This method can be extended to test generation and redundancy identification. The extended method constructs the product machine of two FSM's to be compared, and reachability analysis is performed by traversing the product machine to find any difference in I/O behavior. When an output difference is detected, the information obtained by reachability analysis is used to generate a test sequence. This method is complete and it generates one of the shortest possible test sequences for a given fault. However, applying this method indiscriminately for all faults may result in unnecessary waste of computer resources. In this paper, we present an efficient method based on reachability analysis of the fault-free machine (three-phase ATPG) in addition to the powerful but more resource-demanding product machine traversal. We report on the application of these algorithms to the problems of generating test sequences, identifying redundancies, and removing redundancies.

引用

页码：935 / 945

页数：11

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