USING SEMATECH ELECTRICAL TEST STRUCTURES IN ASSESSING PLASMA-INDUCED DAMAGE IN POLY ETCHING

The use of capacitive antenna structures to assess process-induced charging damage is well documented. A description of a subset of the SEMATECH process-induced damage effect revealer (SPIDER) module set is given in this report. SPIDER utilizes various sizes and shapes of antenna structures tied to transistors. In this investigation, the evaluation of plasma etch damage, primarily from the gate polysilicon etch, is reported using 0.5 mu m n-channel metal-oxide-semiconductor (NMOS) antenna transistor. Damage appears to occur at the gate oxide bulk and interface. A portion of this damage is not measured after post-metallization annealing unless activated by electrical stress or some subsequent processing. The damage does not correlate with transistor antenna area present during the poly-Si etch. However, a correlation is observed for transistor parameters measured after activation by Fowler-Nordheim stress. This latency may be attributed to hydrogen passivation. A damage model is presented here.