50-MHZ PHASE-LOCKED AND FREQUENCY-LOCKED LOOP

被引：19

作者：

CORDELL, RR

FORNEY, JB

DUNN, CN

GARRETT, WG

机构：

[1] BELL TEL LABS INC,LIGHTWAVE CIRCUITS GRP,HOLMDEL,NJ 07733

[2] BELL TEL LABS INC,DEPT INTEGRATED CIRCUITS,READING,PA 19604

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1979年 / 14卷 / 06期

关键词：

D O I：

10.1109/JSSC.1979.1051309

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A monolithic phase/frequency-locked loop has been developed for operation at up to 50 MHz. The loop combines wide capture range and narrow bandwidth, making it ideal for timing recovery in digital transmission systems: The 24-pin device features an electronically-tuned, voltage-controlled LC oscillator and includes the input differentiation and full-wave- rectification circuitry required for clock recovery from unipolar nonreturn-to-zero (NRZ) data. Copyright © 1979 by The Institute of Electrical and Electronics Engineers, Inc.

引用

页码：1003 / 1010

页数：8

共 9 条

[1]

BELLISIO JA, 1976, JUN P ICC 76, V1, P10

[2] HIGHLY STABLE VCO FOR APPLICATION IN MONOLITHIC PHASE-LOCKED LOOPS [J].