EFFICIENT ALGORITHMS FOR SCHEDULING SEMICONDUCTOR BURN-IN OPERATIONS

被引:382
作者
LEE, CY
UZSOY, R
MARTINVEGA, LA
机构
[1] PURDUE UNIV,W LAFAYETTE,IN 47907
[2] NATL SCI FDN,DIV DESIGN & MFG SYST,WASHINGTON,DC 20550
关键词
D O I
10.1287/opre.40.4.764
中图分类号
C93 [管理学];
学科分类号
12 ; 1201 ; 1202 ; 120202 ;
摘要
In this paper, we study the problem of scheduling semiconductor bum-in operations, where burn-in ovens are modeled as batch processing machines. A batch processing machine is one that can process up to B jobs simultaneously. The processing time of a batch is equal to the largest processing time among all jobs in the batch. We present efficient dynamic programming-based algorithms for minimizing a number of different performance measures on a single batch processing machine. We also present heuristics for a number of problems concerning parallel identical batch processing machines and we provide worst case error bounds.
引用
收藏
页码:764 / 775
页数:12
相关论文
共 26 条
[1]   BATCHING AND SCHEDULING JOBS ON BATCH AND DISCRETE PROCESSORS [J].
AHMADI, JH ;
AHMADI, RH ;
DASU, S ;
TANG, CS .
OPERATIONS RESEARCH, 1992, 40 (04) :750-763
[2]   A COMPARISON OF DUE-DATE SELECTION-RULES [J].
BAKER, KR ;
BERTRAND, JWM .
AIIE TRANSACTIONS, 1981, 13 (02) :123-131
[3]   DEVELOPMENT AND IMPLEMENTATION OF A SCHEDULING SYSTEM FOR A WAFER FABRICATION FACILITY [J].
BITRAN, GR ;
TIRUPATI, D .
OPERATIONS RESEARCH, 1988, 36 (03) :377-395
[4]   PLANNING AND SCHEDULING FOR EPITAXIAL WAFER PRODUCTION FACILITIES [J].
BITRAN, GR ;
TIRUPATI, D .
OPERATIONS RESEARCH, 1988, 36 (01) :34-49
[5]   EMPIRICAL-EVALUATION OF A QUEUING NETWORK MODEL FOR SEMICONDUCTOR WAFER FABRICATION [J].
CHEN, H ;
HARRISON, JM ;
MANDELBAUM, A ;
VANACKERE, A ;
WEIN, LM .
OPERATIONS RESEARCH, 1988, 36 (02) :202-215
[6]   A MODEL FOR WAFER FABRICATION DYNAMICS IN INTEGRATED-CIRCUIT MANUFACTURING [J].
DAYHOFF, JE ;
ATHERTON, RW .
IEEE TRANSACTIONS ON SYSTEMS MAN AND CYBERNETICS, 1987, 17 (01) :91-100
[7]  
Deb R. K., 1973, Advances in Applied Probability, V5, P340, DOI 10.2307/1426040
[8]  
Garey MR., 1979, COMPUTERS INTRACTABI
[9]   CLOSED-LOOP JOB RELEASE CONTROL FOR VLSI CIRCUIT MANUFACTURING [J].
GLASSEY, CR ;
RESENDE, MGC .
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 1988, 1 (01) :36-46
[10]   DYNAMIC BATCHING HEURISTIC FOR SIMULTANEOUS PROCESSING [J].
GLASSEY, CR ;
WENG, WW .
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 1991, 4 (02) :77-82