A NEURAL NETWORK DESIGN FOR CIRCUIT PARTITIONING

被引：9

作者：

YIH, JS

MAZUMDER, P

机构：

[1] Department ot Electrical Engineering and Computer Science, University of Michigan, Ann Arbor

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1990年 / 9卷 / 12期

基金：

美国国家科学基金会;

关键词：

D O I：

10.1109/43.62771

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a neural network model for circuit bipartitioning. The massive parallelism of neural nets has been successfully exploited to balance the partitions of a circuit and to reduce the external wiring between the partitions. The experimental results obtained by neural nets are found to be comparable with those achieved by the Fiduccia and Mattheyses algorithm. The proposed approach can be implemented in hardware to accelerate the time consuming partitioning procedures. © 1990 IEEE

引用

页码：1265 / 1271

页数：7

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