4096-B ONE-TRANSISTOR PER BIT RANDOM-ACCESS MEMORY WITH INTERNAL TIMING AND LOW DISSIPATION

被引:6
作者
BOONSTRA, L [1 ]
LAMBRECHTSE, CW [1 ]
SALTERS, RHW [1 ]
机构
[1] PHILIPS RES LABS, EINDHOVEN, NETHERLANDS
关键词
D O I
10.1109/JSSC.1973.1050408
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:305 / 310
页数:6
相关论文
共 5 条
[1]  
COHEN L, 1971, ELECTRONICS 0802, P69
[2]   SURFACE-CHARGE RANDOM-ACCESS MEMORY SYSTEM [J].
ENGELER, WE ;
TIEMANN, JJ ;
BAERTSCH, RD .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1972, SC 7 (05) :330-&
[3]   ELIMINATING THRESHOLD LOSSES IN MOS CIRCUITS BY VARACTOR BOOTSTRAPPING [J].
JOYNSON, RE ;
MUNDY, JL ;
BURGESS, JF ;
NEUGEBAU.CA .
PROCEEDINGS OF THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, 1971, 59 (09) :1365-&
[4]  
KOOI E, 1971, PHILIPS RES REP, V26, P166
[5]   STORAGE ARRAY AND SENSE-REFRESH CIRCUIT FOR SINGLE-TRANSISTOR MEMORY CELLS [J].
STEIN, KU ;
SIHLING, A ;
DOERING, E .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1972, SC 7 (05) :336-&