INALAS/INGAAS HETEROSTRUCTURE FETS PROCESSED WITH SELECTIVE REACTIVE-ION-ETCHING GATE-RECESS TECHNOLOGY

被引:14
作者
AGARWALA, S
NUMMILA, K
ADESIDA, I
CANEAU, C
BHAT, R
机构
[1] UNIV ILLINOIS, DEPT ELECT & COMP ENGN, URBANA, IL 61801 USA
[2] BELL COMMUN RES INC, RED BANK, NJ 07701 USA
基金
美国国家科学基金会;
关键词
D O I
10.1109/55.244718
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A newly developed highly selective reactive-ion-etching process based on HBr plasma has been applied as a gate-recess technique in the fabrication of InAlAs/InGaAs heterostructure FET's. A typical 0.75-mum gate-length transistor exhibited a threshold voltage of -1.0 V, a maximum extrinsic transconductance of 600 mS/mm, an extrinsic current-gain cutoff frequency of 37 GHz, and a maximum frequency of oscillation of 90 GHz. These dc and RF device parameters compare favorably with that of a corresponding device gate-recessed with a selective wet-etching technique.
引用
收藏
页码:425 / 427
页数:3
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