A 1-V TFT-LOAD SRAM USING A 2-STEP WORD-VOLTAGE METHOD

被引：15

作者：

ISHIBASHI, K

TAKASUGI, K

YAMANAKA, T

HASHIMOTO, T

SASAKI, K

机构：

[1] Central Research Laboratory, Hitachi Ltd., Kokubunji-shi, Tokyo 185

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1992年 / 27卷 / 11期

关键词：

D O I：

10.1109/4.165331

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 1-V SRAM using a TFT load cell was developed. Key circuits for obtaining the low-voltage operation are a two-step word-voltage (TSW) method, a submicroampere boosted-level generator using a multivibrator, and a sense amplifier using low-threshold MOSFET's. An access time of 250 ns and a standby current of 0.23 muA were achieved for a 4-kb test chip using a 10.2-mum2 TFT-load cell. This technology is applicable for high-density and single-battery operational SRAM's.

引用

页码：1519 / 1524

页数：6

共 6 条

[1] AN ALPHA-IMMUNE, 2-V SUPPLY VOLTAGE SRAM USING A POLYSILICON PMOS LOAD CELL [J].