MINIMIZATION OF THE OFFSET VOLTAGE IN HETEROJUNCTION DIPOLAR TRANSISTORS BY USING A THICK SPACER

被引:12
作者
WANG, Q [1 ]
YANG, ES [1 ]
CHEN, YK [1 ]
SIVCO, D [1 ]
CHO, AY [1 ]
机构
[1] AT&T BELL LABS,MURRAY HILL,NJ 07974
关键词
D O I
10.1063/1.109104
中图分类号
O59 [应用物理学];
学科分类号
摘要
We have successfully fabricated and characterized two-dimensional electron gas emitter heterojunction bipolar transistors (2DEG emitter HBTs) of AlInAs/InGaAs and AlGaAs/GaAs compound materials. With a 50 nm thick undoped InGaAs spacer employed in the emitter junction, the offset voltage of the AlInAs/InGaAs HBT is reduced from 500 to 70 mV. Experimental data of the offset voltage obtained at different spacer thickness show that a spacer of 30 nm would be optimum for both AlGaAs/GaAs and AlInAs/InGaAs HBTs. This is basically in agreement with the numerical calculation of the electron sheet density of the 2DEG. The reduction of the offset voltage by using a 2DEG emitter is particularly important for the AlInGa/InGaAs or InP/InGaAs HBTs, since the breakdown voltage of these devices is usually low and the composition grading in the emitter is either very complicated or not applicable.
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页码:3129 / 3131
页数:3
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