70-MHZ 2-MU-M CMOS BIT-LEVEL SYSTOLIC ARRAY MEDIAN FILTER

A novel algorithm for VLSI median filtering of one-dimensional signals of complexity linearly dependent on the filter window length is described in this paper. The algorithm is implemented as a bit-level systolic array (BLSA), in order to achieve a high performance. A single-chip median filter characterized by a window length of 25 8-b samples, and by the operation on three interleaved independent sequences for a total of 75 samples, is also presented as a demonstrator. The throughput relevant to one sequence is 1/3 in this chip, whereas the theoretical maximum allowed by the algorithm is 1/2. Prototypes designed with a 2-mum CMOS technology have been successfully tested at a clock frequency over 70 MHz.