PARALLEL BIT-LEVEL PIPELINED VLSI DESIGNS FOR HIGH-SPEED SIGNAL-PROCESSING

[1] BAKOGLU H, 1986, OCT P INT C COMP DES, P118

[2] OPTIMAL INTERCONNECTION CIRCUITS FOR VLSI [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (05) : 903 - 909

[3] COMPLETELY-PIPELINED ARCHITECTURES FOR DIGITAL SIGNAL-PROCESSING [J]. IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND SIGNAL PROCESSING, 1983, 31 (04): : 1016 - 1023

[4] A NOTE ON FREE ACCUMULATION IN VLSI FILTER ARCHITECTURES [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1985, 32 (03): : 291 - 296

[5] A VLSI LAYOUT FOR A PIPELINED DADDA MULTIPLIER [J]. ACM TRANSACTIONS ON COMPUTER SYSTEMS, 1983, 1 (02): : 157 - 174

[6] OPTIMAL CHOICE OF INTERMEDIATE LATCHING TO MAXIMIZE THROUGHPUT IN VLSI CIRCUITS [J]. IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND SIGNAL PROCESSING, 1984, 32 (01): : 28 - 33

[7] CAPPELLO PR, 1982, SEP P IEEE INT C CIR, P570

[8] CORRY A, 1983, P IEEE S CIRCUITS SY, P522

[9] Evans R. A., 1983, VLSI '83. Proceedings of the IFIP TC WG 10.5 International Conference on Very Large Scale Integration, P227

[10] FISHER AL, 1985, IEEE T COMPUT, V34, P734, DOI 10.1109/TC.1985.1676619

[1] BAKOGLU H, 1986, OCT P INT C COMP DES, P118

[2] OPTIMAL INTERCONNECTION CIRCUITS FOR VLSI [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (05) : 903 - 909

[3] COMPLETELY-PIPELINED ARCHITECTURES FOR DIGITAL SIGNAL-PROCESSING [J]. IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND SIGNAL PROCESSING, 1983, 31 (04): : 1016 - 1023

[4] A NOTE ON FREE ACCUMULATION IN VLSI FILTER ARCHITECTURES [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1985, 32 (03): : 291 - 296

[5] A VLSI LAYOUT FOR A PIPELINED DADDA MULTIPLIER [J]. ACM TRANSACTIONS ON COMPUTER SYSTEMS, 1983, 1 (02): : 157 - 174

[6] OPTIMAL CHOICE OF INTERMEDIATE LATCHING TO MAXIMIZE THROUGHPUT IN VLSI CIRCUITS [J]. IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND SIGNAL PROCESSING, 1984, 32 (01): : 28 - 33

[7] CAPPELLO PR, 1982, SEP P IEEE INT C CIR, P570

[8] CORRY A, 1983, P IEEE S CIRCUITS SY, P522

[9] Evans R. A., 1983, VLSI '83. Proceedings of the IFIP TC WG 10.5 International Conference on Very Large Scale Integration, P227

[10] FISHER AL, 1985, IEEE T COMPUT, V34, P734, DOI 10.1109/TC.1985.1676619