A 65-NS 4-MBIT CMOS DRAM WITH A TWISTED DRIVELINE SENSE AMPLIFIER

被引：6

作者：

KIMURA, K ^{[1
]}

SHIMOHIGASHI, K ^{[1
]}

ETOH, J ^{[1
]}

ISHIHARA, M ^{[1
]}

MIYAZAWA, K ^{[1
]}

SHIMIZU, S ^{[1
]}

SAKAI, Y ^{[1
]}

YAGI, K ^{[1
]}

机构：

[1] HITACHI LTD,CTR DEVICE DEV,KOKUBUNJI,TOKYO 185,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1987年 / 22卷 / 05期

关键词：

65-NS 4-MBIT DRAM - COMPLEMENTARY MOS (CMOS) - DYNAMIC RANDOM ACCESS MEMORY (DRAM) - MULTIPHASE DRIVE (MPD) CIRCUIT - TWISTED DRIVELINE SENSE-AMPLIFIER (TDSA);

D O I：

10.1109/JSSC.1987.1052795

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：651 / 656

页数：6

共 9 条

[1] EATON S, 1981, FEB ISSCC, P84
[2] ITOH K, 1983, IEE PROC-I, V130, P127, DOI 10.1049/ip-i-1.1983.0024
[3] ITOH K, 1984, FEB IEEE INT SOL STA, P282
[4] POWER REDUCTION TECHNIQUES IN MEGABIT DRAMS
KIMURA, K
ITOH, K
HORI, R
ETOH, J
KAWAJIRI, Y
KAWAMOTO, H
SATO, K
MATSUMOTO, T
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (03) : 381 - 389
[5] KOYANAGI M, 1978, DEC IEDM TECH DIG, P348
[6] LEE JM, 1979, FEB ISSCC, P142
[7] HALF-VDD BIT-LINE SENSING SCHEME IN CMOS DRAMS
LU, NCC
CHAO, HH
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1984, 19 (04) : 451 - 454
[8] SHIMOHIGASHI K, 1987, FEB ISSCC, P18
[9] WHITESIDE F, 1986, FEB ISSCC, P48

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