HALF-VDD BIT-LINE SENSING SCHEME IN CMOS DRAMS

[1] 16 384-BIT DYNAMIC RAM [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1976, 11 (05) : 570 - 574

[2] A SYSTEM SOLUTION TO THE MEMORY SOFT ERROR PROBLEM [J]. IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1980, 24 (03) : 390 - 397

[3] CHWANG R, 1983, P IEEE ISSCC, P56

[4] EATON SS, 1979, P IEEE ISSCC, P144

[5] PERIPHERAL CIRCUITS FOR ONE TRANSISTOR CELL MOS RAMS [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1975, 10 (05) : 255 - 261

[6] A 5 V-ONLY 64K DYNAMIC RAM BASED ON HIGH S-N DESIGN [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1980, 15 (05) : 846 - 854

[7] SHIMOHIGASHI K, 1982, IEEE J SOLID STATE C, V17, P344

[8] 1-MIL2 SINGLE-TRANSISTOR MEMORY CELL IN N SILICON-GATE TECHNOLOGY [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1973, SC 8 (05) : 319 - 323

[9] STORAGE ARRAY AND SENSE-REFRESH CIRCUIT FOR SINGLE-TRANSISTOR MEMORY CELLS [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1972, SC 7 (05) : 336 - &

[1] 16 384-BIT DYNAMIC RAM [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1976, 11 (05) : 570 - 574

[2] A SYSTEM SOLUTION TO THE MEMORY SOFT ERROR PROBLEM [J]. IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1980, 24 (03) : 390 - 397

[3] CHWANG R, 1983, P IEEE ISSCC, P56

[4] EATON SS, 1979, P IEEE ISSCC, P144

[5] PERIPHERAL CIRCUITS FOR ONE TRANSISTOR CELL MOS RAMS [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1975, 10 (05) : 255 - 261

[6] A 5 V-ONLY 64K DYNAMIC RAM BASED ON HIGH S-N DESIGN [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1980, 15 (05) : 846 - 854

[7] SHIMOHIGASHI K, 1982, IEEE J SOLID STATE C, V17, P344

[8] 1-MIL2 SINGLE-TRANSISTOR MEMORY CELL IN N SILICON-GATE TECHNOLOGY [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1973, SC 8 (05) : 319 - 323

[9] STORAGE ARRAY AND SENSE-REFRESH CIRCUIT FOR SINGLE-TRANSISTOR MEMORY CELLS [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1972, SC 7 (05) : 336 - &