A 16-MB FLASH EEPROM WITH A NEW SELF-DATA-REFRESH SCHEME FOR A SECTOR ERASE OPERATION

被引：33

作者：

ATSUMI, S

KURIYAMA, M

UMEZAWA, A

BANBA, H

NARUKE, K

YAMADA, S

OHSHIMA, Y

OSHIKIRI, M

HIURA, Y

YAMANE, T

YOSHIKAWA, K

机构：

[1] TOSHIBA MICROELECTR CORP,KAWASAKI 210,JAPAN

[2] TOSHIBA CO LTD,DIV MEMORY,KAWASAKI 210,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1994年 / 29卷 / 04期

关键词：

Flash EEPROM - Internal voltage generator - Memory cell - Negative gate biased scheme - Read operation failure - Row decoder circuit - Sector erase operation - Self convergence method - Self data refresh operation;

D O I：

10.1109/4.280696

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 16-Mb flash EEPROM has been developed based on the 0.6-mum triple-well double-poly-si single-metal CMOS technology. A compact row decoder circuit for a negative gate biased erase operation has been designed to obtain the sector erase operation. A self-data-refresh scheme has been developed to overcome the drain-disturb problem for unselected sector cells. A self-convergence method after erasure is applied in this device to over-come the overerase problem that causes read operation failure. Both the self-data-refresh operation and the self-convergence method are verified to be involved in the autoerase operation. Internal voltage generators independent of the external voltage supply and temperature has been developed. The cell size is 2.0 mum x 1.7 mum, and the die size has resulted in 7.7 mm x 17.32 mm.

引用

页码：461 / 469

页数：9

共 17 条

[1]

ATSUMI S, 1990, ISSCC, P58

[2]

HADDAD S, 1990, IEEE J SOLID STATE C, V25, P514

[3]

Itoh Y., 1989, ISSCC DIG TECH PAPER, P134

[4] A 5-V-ONLY 16-MB FLASH MEMORY WITH SECTOR ERASE MODE [J].

JINBO, T ;

NAKATA, H ;

HASHIMOTO, K ;

WATANABE, T ;

NINOMIYA, K ;

URAI, T ;

KOIKE, M ;

SATO, T ;

KODAMA, N ;

OYAMA, K ;

OKAZAWA, T .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (11) :1547-1554

[5]

KUME H, 1991, S VLSI TECHNOLOGY, P75

[6]

KYNETT VN, 1988, IEEE INT SOL STAT CI, P132

[7] A 256-KBIT FLASH E2PROM USING TRIPLE-POLYSILICON TECHNOLOGY [J].

MASUOKA, F ;

ASANO, M ;

IWAHASHI, H ;

KOMURO, T ;

TOZAWA, N ;

TANAKA, S .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (04) :548-552

[8]

NAKAYAMA T, 1991, ISSCC DIGEST TECHNIC, P260

[9]

Ohshima Y., 1990, International Electron Devices Meeting 1990. Technical Digest (Cat. No.90CH2865-4), P95, DOI 10.1109/IEDM.1990.237218

[10]

OHTSUKA N, 1991, ISSCC, P262

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