MODULAR, HIGH-SPEED SERIAL PIPELINE MULTIPLIER FOR DIGITAL SIGNAL-PROCESSING

被引：9

作者：

BALDWIN, GL

MORRIS, BL

FRASER, DB

TRETOLA, AR

机构：

[1] BELL TEL LABS,ALLENTOWN,PA 18105

[2] BELL TEL LABS INC,MURRAY HILL,NJ 07974

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1978年 / 13卷 / 03期

关键词：

D O I：

10.1109/JSSC.1978.1051064

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：400 / 408

页数：9

共 14 条

[1] DIGITAL MULTIPLIER POWER ESTIMATES [J].

BAUGH, CR ;

WOOLEY, BA .

IEEE TRANSACTIONS ON COMMUNICATIONS, 1975, 23 (11) :1287-1288

[2]

BAUGH CR, UNPUBLISHED

[3]

DASH S, 1973, SEMICONDUCTOR SILICO

[4]

FRASER D, UNPUBLISHED

[5] SPECIAL-PURPOSE HARDWARE FOR DIGITAL FILTERING [J].

FREENY, SL .

PROCEEDINGS OF THE IEEE, 1975, 63 (04) :633-648

[6] CMOS-SOS SERIAL-PARALLEL MULTIPLIER [J].

HAMPEL, D ;

MCGUIRE, KE ;

PROST, KJ .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1975, 10 (05) :307-314

[7] AN APPROACH TO IMPLEMENTATION OF DIGITAL FILTERS [J].

JACKSON, LB ;

KAISER, JF ;

MCDONALD, HS .

IEEE TRANSACTIONS ON AUDIO AND ELECTROACOUSTICS, 1968, AU16 (03) :413-&

[8] LOW-POWER, BIPOLAR, 2S COMPLEMENT SERIAL PIPELINE MULTIPLIER CHIP [J].

KANE, J .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1976, 11 (05) :669-678

[9]

LYON RF, 1976, IEEE T COMPUT, V12, P418

[10]

MCIVER GW, 1974 ISSCC DIG TECH, V17, P54

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