VERIFICATION OF THE IBM RISC SYSTEM 6000 BY A DYNAMIC BIASED PSEUDORANDOM TEST PROGRAM GENERATOR

被引：33

作者：

AHARON, A ^{[1
]}

BARDAVID, A ^{[1
]}

DORFMAN, B ^{[1
]}

GOFMAN, E ^{[1
]}

LEIBOWITZ, M ^{[1
]}

SCHWARTZBURD, V ^{[1
]}

机构：

[1] IBM CORP,DIV ADV WORKSTN,AUSTIN,TX 78758

来源：

IBM SYSTEMS JOURNAL | 1991年 / 30卷 / 04期

关键词：

D O I：

10.1147/sj.304.0527

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Verification of a computer that implements a new architecture is especially difficult since no approved functional test cases are available. The logic design of the IBM RISC System/6000TM was verified mainly by a specially developed random test program generator (RTPG), which was used from the early stages of the design until its succesful completion. APL was chosen for the RISC System/6000 RTPG implementation after considering the suitability of this programming language for modeling computer architectures, the very tight schedule, and the highly changeable environment in which RTPG would operate.

引用

页码：527 / 538

页数：12

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