A 30-MHZ MIXED ANALOG DIGITAL SIGNAL PROCESSOR

被引：2

作者：

TAKEUCHI, S ^{[1
]}

KOUNO, H ^{[1
]}

HAYASHI, Y ^{[1
]}

MAEDA, A ^{[1
]}

OKADA, K ^{[1
]}

YAZAWA, N ^{[1
]}

机构：

[1] MITSUBISHI ELECTR CO,CTR ASIC DESIGN ENGN,ITAMI,HYOGO 664,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1990年 / 25卷 / 06期

关键词：

D O I：

10.1109/4.62180

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 30-MHz mixed analog and digital signal processor has been designed using an efficient architecture. The processor is based on the multiplying encoder and is suitable for performing both high-speed A/D conversion and digital filtering function in a single chip. The device can resolve the input with 8 b at 30 megasamples per second (MSPS) and perform 28 multiply and 28 add operations per sample under typical conditions. The processor designed for a 28-tap programmable FIR filter with analog input signal can be used for waveform shaping of the MODEM to obtain the desired transmission performance for business satellite communication and mobile communication. The chip is fabricated in a 1-μpm double-polysilicon and double-metal CMOS technology. The chip size is 9.73x8.14 mm2 and the chip operates with a single +5.0-V power supply. Typical power dissipation is 950 mW; 330 mW is dissipated in analog and 620 mW is in the digital block. © 1990 IEEE

引用

页码：1458 / 1469

页数：12