A PROGRAMMABLE ANALOG CELLULAR NEURAL-NETWORK CMOS CHIP FOR HIGH-SPEED IMAGE-PROCESSING

A high speed analog image processor chip is presented, It is based on the cellular neural network architecture. The implementation of an analog programmable CNN-chip in a standard CMOS technology is discussed. The control parameters or templates in all cells are under direct user control and are tunable over a continuous value range from 1/4 to 4. This tuning property is implemented with a compact current scaling circuit based on MOS transistors operating in the linear region, A 4 x 4 CNN prototype system has been designed in a 2.4 mu m CMOS technology and successfully tested, The cell density is 380 cells/cm(2) and the cell time constant is 10 mu s. The current drain for a typical template is 40 mu A/cell. The real-time image processing capabilities of the system are demonstrated, From this prototype it is estimated that a 128 x 128 fully programmable analog image processing system can be integrated on a single chip using a standard digital submicron CMOS technology, This work demonstrates that powerfull high speed programmable analog processing systems can be built using standard CMOS technologies.