DIRECT EVIDENCE SUPPORTING THE PREMISES OF A TWO-DIMENSIONAL DIODE MODEL FOR THE PARASITIC THYRISTOR IN CMOS CIRCUITS BUILT ON THIN EPI

被引：6

作者：

CHATTERJEE, A

SEITCHIK, JA

CHERN, JH

YANG, P

WEI, CC

机构：

来源：

IEEE ELECTRON DEVICE LETTERS | 1988年 / 9卷 / 10期

关键词：

D O I：

10.1109/55.17827

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：509 / 511

页数：3

共 10 条

[1]

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HERLET, A ;

RAITHEL, K .

SOLID-STATE ELECTRONICS, 1966, 9 (11-1) :1089-&

[3]

Lai F. S., 1985, International Electron Devices Meeting. Technical Digest (Cat. No. 85CH2252-5), P513

[4]

Lewis A. G., 1986, 1986 Symposium on VLSI Technology. Digest of Technical Papers, P23

[5]

Niitsu Y., 1985, International Electron Devices Meeting. Technical Digest (Cat. No. 85CH2252-5), P509

[6]

PINTO MR, 1984, PISCES 2 USERS MANUA

[7] HIGH HOLDING VOLTAGE C-MOS TECHNOLOGY WITH LIGHTLY DOPED SOURCE AND DRAIN REGIONS [J].

RICCO, B ;

SANGIORGI, E ;

FERRIANI, G .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1987, 34 (04) :810-816

[8] AN ANALYTIC MODEL OF HOLDING VOLTAGE FOR LATCH-UP IN EPITAXIAL CMOS [J].

SEITCHIK, JA ;

CHATTERJEE, A ;

YANG, P .

IEEE ELECTRON DEVICE LETTERS, 1987, 8 (04) :157-159

[9]

SON I, 1988, IEEE T ELECTRON DEVI, V35, P45

[10]

Zappe H. P., 1985, International Electron Devices Meeting. Technical Digest (Cat. No. 85CH2252-5), P517

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