HIGH HOLDING VOLTAGE C-MOS TECHNOLOGY WITH LIGHTLY DOPED SOURCE AND DRAIN REGIONS

被引：7

作者：

RICCO, B

SANGIORGI, E

FERRIANI, G

机构：

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1987年 / 34卷 / 04期

关键词：

D O I：

10.1109/T-ED.1987.23000

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：810 / 816

页数：7

共 12 条

[1]

ESTREICH DB, 1980, G2019 STANF EL LAB

[2]

Ghandhi SK, 1977, SEMICONDUCTOR POWER

[3]

HO CP, 1983, SUPREM 3 PROGRAM INT

[4] METHOD FOR DETERMINING THE EMITTER AND BASE SERIES RESISTANCES OF BIPOLAR-TRANSISTORS [J].

NING, TH ;

TANG, DD .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1984, 31 (04) :409-412

[5] AN EFFICIENT NUMERICAL-MODEL OF CMOS LATCH-UP [J].

PINTO, MR ;

DUTTON, RW .

IEEE ELECTRON DEVICE LETTERS, 1983, 4 (11) :414-417

[6]

PINTO MR, 1984, PISCES 2 POISSON CON

[7] TWO-DIMENSIONAL NUMERICAL-ANALYSIS OF LATCHUP IN A VLSI CMOS TECHNOLOGY [J].

SANGIORGI, EC ;

PINTO, MR ;

SWIRHUN, SE ;

DUTTON, RW .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (10) :2117-2130

[8]

Swirhun S., 1984, International Electron Devices Meeting. Technical Digest (Cat. No. 84CH2099-0), P402

[9]

SWIRHUN SE, 1985, IEEE T ELECTRON DEV, V32, P194, DOI 10.1109/T-ED.1985.21929

[10]

Taur Y., 1984, International Electron Devices Meeting. Technical Digest (Cat. No. 84CH2099-0), P398

← 1 2 →