A 288-KB FULLY PARALLEL CONTENT ADDRESSABLE MEMORY USING A STACKED-CAPACITOR CELL STRUCTURE

This paper describes a 288-kb (8K words x 36 b) fully parallel content addressable memory (CAM) LSI using a compact dynamic CAM cell with a stacked-capacitor structure and a novel hierarchical priority encoder. The stacked-capacitor structure results in a very compact dynamic CAM cell (66 mum2) which is operationally stable. The novel hierarchical priority encoder reduces the circuit area and power dissipation. In addition, a new priority decision circuit is introduced. The chip size is 10.3 x 12.0 mm2 using a 0.8-mum CMOS process technology. A typical search cycle time of 150 ns and a maximum power dissipation of 1.1 W have been obtained using circuit simulation. In fabricated CAM chips, we have verified the performance of a search operation at a 170-ns cycle and have achieved a typical read/write cycle time of 120 ns. This CAM LSI performs large-scale search operations very efficiently, and therefore, has the possibility of broad applications to high-performance artificial intelligence machines and data-base systems.