INHERENT PATTERN JITTER OF STM-64 FORMAT SIGNAL AND A REDUCTION METHOD

被引：2

作者：

ONO, T ^{[1
]}

YAMABAYASHI, Y ^{[1
]}

HAGIMOTO, K ^{[1
]}

HOHKAWA, K ^{[1
]}

机构：

[1] NIPPON TELEGRAPH & TEL PUBL CORP, LSI LABS, ATSUGI, KANAGAWA 24301, JAPAN

来源：

ELECTRONICS LETTERS | 1992年 / 28卷 / 22期

关键词：

DIGITAL TRANSMISSION; JITTER;

D O I：

10.1049/el:19921353

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The inherent pattern jitter of the STM-64 format signal is found to be increased by the DC level fluctuation of incoming data and the output power variation of the timing tank in the section overhead bytes which become longer than the time constant of the timing tank. This pattern jitter is reported to be successfully suppressed by using an already proposed timing recovery circuit with a 1/2T differentiator, which operates as a pattern transformer.

引用

页码：2110 / 2112

页数：3

共 3 条

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BYRNE, CJ ;

ROBINSON, DB ;

KARAFIN, BJ .

BELL SYSTEM TECHNICAL JOURNAL, 1963, 42 (06) :2679-+

[2] REDUCTION OF RMS JITTER AND PHASE DEVIATION IN 10 GBIT/S TIMING RECOVERY CIRCUIT USING MONOLITHIC ICS [J].

ONO, T ;

HAGIMOTO, K ;

NAKAMURA, M ;

ISHIHARA, N ;

KIKUCHI, H .

ELECTRONICS LETTERS, 1992, 28 (04) :403-405

[3] REDUCTION OF SYSTEMATIC JITTER IN A TRANSMISSION CHAIN WITH DIGITAL REGENERATORS [J].

ZEGERS, LE .

IEEE TRANSACTIONS ON COMMUNICATION TECHNOLOGY, 1967, CO15 (04) :542-&

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