REDUCTION OF RMS JITTER AND PHASE DEVIATION IN 10 GBIT/S TIMING RECOVERY CIRCUIT USING MONOLITHIC ICS

被引：3

作者：

ONO, T

HAGIMOTO, K

NAKAMURA, M

ISHIHARA, N

KIKUCHI, H

机构：

[1] NIPPON TELEGRAPH & TEL PUBL CORP, ELECTR TECHNOL CORP, ATSUGI, KANAGAWA 24303, JAPAN

[2] NIPPON TELEGRAPH & TEL PUBL CORP, LSI LABS, ATSUGI, KANAGAWA 24303, JAPAN

来源：

ELECTRONICS LETTERS | 1992年 / 28卷 / 04期

关键词：

OPTICAL COMMUNICATION; OPTICAL TRANSMISSION; CIRCUIT DESIGN;

D O I：

10.1049/el:19920253

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 10Gbit/s timing recovery circuit using GaAs IC technologies is presented. A jitter suppression method using two cascaded differentiators is proposed. The phase deviation characteristics of a timing recovery circuit for mark density variation are also discussed.

引用

页码：403 / 405

页数：3

共 6 条

[1] STATISTICAL PROPERTIES OF TIMING JITTER IN A PAM TIMING RECOVERY SCHEME [J].