AN SEU RESISTANT 256K SOI SRAM

被引:33
作者
HITE, LR
LU, H
HOUSTON, TW
HURTA, DS
BAILEY, WE
机构
[1] Texas Instruments Inc., Dallas
关键词
D O I
10.1109/23.211411
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A novel SOI memory cell has been implemented in a 1.0-mum 256K SRAM with a 20-ns worst-case minimum WRITE time at +125-degrees-C, and providing a single event upset (SEU) immunity of less than 1 x 10(-10) errors/bit-day over temperature. The worst-case supply voltage for SEU was found to be 5.5 V, rather than the usually assumed 4.5 V. This is attributed to bipolar effects of the SOI transistor, and thus has possible implications for SEU testing of all SOI memories.
引用
收藏
页码:2121 / 2125
页数:5
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