共 21 条
- [21] [No title captured]
A PARALLEL ARCHITECTURE FOR PROBABILISTIC RELAXATION OPERATIONS ON IMAGES
被引：3
作者：
CHEN, Z
LIN, SY
CHEN, YY
机构：
[1] Department of Computer Science and Information Engineering, National Chiao Tung University, Hsinchu
关键词：
CAD simulations;
Combiner;
Linear systolic array;
parallel architecture;
Performance evaluation;
Probabilistic relaxation;
Processing element;
VLSI chip;
D O I：
10.1016/0031-3203(90)90039-N
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ;
0812 ;
0835 ;
1405 ;
摘要：
The design of a parallel architecture for executing probabilistic relaxation operations on two dimensional images is addressed. First of all, the concerned relaxation process is divided into three different parallel operations, i.e. systolic, simultaneous, and pipelined. All these parallel operations are mapped onto a linear array architecture that runs smoothly without any bottleneck in the data flows. The proposed architecture and its components are described. An illustrative running of the relaxation process for an image thresholding application on the architecture is described in some details. The hardware implementation and CAD logic simulation are then given. Finally, performance comparison between the proposed architecture and some existing ones is reported. © 1990.
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页码：637 / 645
页数：9
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