NUMERICAL-ANALYSIS OF DC PERFORMANCE OF SMALL GEOMETRY LATERAL TRANSISTORS

被引：10

作者：

LAST, JD ^{[1
]}

LUCAS, DW ^{[1
]}

SUMERLING, GW ^{[1
]}

机构：

[1] UNIV COLL N WALES, SCH ELECT ENGN SCI, DEAN ST, BANGOR, CAERNS, WALES

来源：

SOLID-STATE ELECTRONICS | 1974年 / 17卷 / 11期

关键词：

D O I：

10.1016/0038-1101(74)90154-3

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：1111 / 1118

页数：8

共 17 条

[1] DETERMINATION OF OPTIMUM ACCELERATING FACTOR FOR SUCCESSIVE OVER-RELAXATION [J].

CARRE, BA .

COMPUTER JOURNAL, 1961, 4 :73-&

[2] CARRIER MOBILITIES IN SILICON EMPIRICALLY RELATED TO DOPING AND FIELD [J].

CAUGHEY, DM ;

THOMAS, RE .

PROCEEDINGS OF THE INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, 1967, 55 (12) :2192-+

[3] INVESTIGATION OF LATERAL TRANSISTORS - DC CHARACTERISTICS [J].

CHOU, S .

SOLID-STATE ELECTRONICS, 1971, 14 (09) :811-&

[4]

COLLINS TW, 1969, TR02461 IBM SYST DEV

[5] DC NUMERICAL MODEL FOR ARBITRARILY BIASED BIPOLAR TRANSISTORS IN 2 DIMENSIONS [J].

DUBOCK, P .

ELECTRONICS LETTERS, 1970, 6 (03) :53-&

[6] NUMERICAL ANALYSIS OF FORWARD AND REVERSE BIAS POTENTIAL DISTRIBUTION IN A 2-DIMENSIONAL P-N JUNCTION WITH APPLICATIONS TO CAPACITANCE CALCULATIONS [J].

DUBOCK, P .

ELECTRONICS LETTERS, 1969, 5 (11) :236-&

[7] A 2-DIMENSIONAL MODEL FOR CALCULATION OF COMMON-EMITTER CURRENT GAINS OF LATERAL P-N-P TRANSISTORS [J].

FULKERSO.DE .

SOLID-STATE ELECTRONICS, 1968, 11 (09) :821-&

[8] A HIGH-PERFORMANCE LATERAL GEOMETRY TRANSISTOR FOR COMPLEMENTARY INTEGRATED CIRCUITS [J].

HILBIBER, DF .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1967, ED14 (07) :381-&

[9]

JENNINGS JE, 1966, IEEE ELECTRON DEVICE

[10] 2-DIMENSIONAL ANALYSIS OF LATERAL-BASE TRANSISTORS [J].

KILPATRI.JA ;

RYAN, WD .

ELECTRONICS LETTERS, 1971, 7 (09) :226-&

← 1 2 →