ERROR CORRECTION TECHNIQUE FOR MULTIVALUED MOS MEMORY

被引：7

作者：

LEE, EKF

GULAK, PG

机构：

[1] VLSI Research Group, Department of Electrical Engineering, University of Toronto, Toronto

来源：

ELECTRONICS LETTERS | 1991年 / 27卷 / 15期

关键词：

MEMORIES; METAL OXIDE SEMICONDUCTOR STRUCTURES AND DEVICES; ERRORS;

D O I：

10.1049/el:19910831

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An error correction technique is proposed to increase the noise margin of a multivalued MOS memory. The stored voltage information is first converted to a binary representation. The noise margin of the store voltage is then increased by storing and comparing the least significant bits of the binary representation.

引用

页码：1321 / 1323

页数：3

共 4 条

[1] IMPLEMENTATION OF A LEARNING KOHONEN NEURON BASED ON A NEW MULTILEVEL STORAGE TECHNIQUE [J].