A SIMPLIFIED LOW-VOLTAGE SMART POWER TECHNOLOGY

被引：2

作者：

BERTA, F

FERNANDEZ, J

HIDALGO, S

GODIGNON, P

REBOLLO, J

MILLAN, J

机构：

[1] Centro Nacional de Microelectrónica CNM, CSIC-UAB, 08193, Bellaterra, Barcelona

来源：

IEEE ELECTRON DEVICE LETTERS | 1991年 / 12卷 / 09期

关键词：

D O I：

10.1109/55.116919

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new self-isolated low-voltage Smart power technology, based on a conventional polysilicon-gate VDMOS process, has been developed for applications where cost is a crucial factor. The low mask count (eight) and the optimization of the VDMOS power device are the main process characteristics. Besides, different devices (high-voltage PMOS, low-voltage CMOS, vertical and lateral n-p-n bipolar transistors, diodes, Zeners, and high-value isolated capacitors) are also fabricated, all MOS transistors being self-aligned to its gate.

引用

页码：465 / 467

页数：3

共 12 条

[1]

Antognetti P., 1986, POWER INTEGRATED CIR

[2] CMOS COMPATIBLE, SELF-BIASED BIPOLAR-TRANSISTOR AIMED AT DETECTING MAXIMUM TEMPERATURE IN A SILICON INTEGRATED-CIRCUIT [J].