A 64-MB DRAM WITH MESHED POWER-LINE

被引：9

作者：

YAMADA, T ^{[1
]}

NAKATA, Y ^{[1
]}

HASEGAWA, J ^{[1
]}

AMANO, N ^{[1
]}

SHIBAYAMA, A ^{[1
]}

SASAGO, M ^{[1
]}

MATSUO, N ^{[1
]}

YABU, T ^{[1
]}

MATSUMOTO, S ^{[1
]}

OKADA, S ^{[1
]}

INOUE, M ^{[1
]}

机构：

[1] MATSUSHITA ELECT IND CO LTD,CENT RES LAB,MORIGUCHI,OSAKA 570,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1991年 / 26卷 / 11期

关键词：

D O I：

10.1109/4.98965

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 64-Mb DRAM has been developed with a meshed power line (MPL) and a quasi distributed sense-amplifier driver (qDSAD) scheme, which realizes high speed (t(RAS) = 50 ns (typical) at V(cc) = 3.3 V) and 16-b I/O [1]. This MPL + qDSAD scheme can reduce sensing delay caused by the metal layer resistance. Furthermore, to suppress crosstalk noise, the V(ss) shield peripheral layout scheme has been introduced, which also widens power line widths. This 64-Mb DRAM is fabricated with 0.4-mu-m CMOS technology using KrF excimer laser lithography. A newly developed memory cell structure, the tunnel-shaped stacked-capacitor cell (TSSC), was adapted to this 64-Mb DRAM.

引用

页码：1506 / 1510

页数：5

共 4 条

[1]

CHIN D, 1989, 1989 S VLSI CIRC, P113

[2] DECODED-SOURCE SENSE AMPLIFIER FOR HIGH-DENSITY DRAMS [J].

OKAMURA, JI ;

OKADA, Y ;

KOYANAGI, M ;

TAKEUCHI, Y ;

YAMADA, M ;

SAKURAI, K ;

IMADA, S ;

SAITO, S .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25 (01) :18-23

[3]

Tani Y., 1990, 1990 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.90CH2874-6), P7, DOI 10.1109/VLSIT.1990.110981

[4]

YAMAMOTO T, 1991, INSTITUTE OF ENVIRONMENTAL SCIENCES, 1991 PROCEEDINGS : 37TH ANNUAL TECHNICAL MEETING, P108

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