AREA MINIMIZATION FOR FLOORPLANS

被引：23

作者：

PAN, PC

LIU, CL

机构：

[1] Department of Computer Science, University of Illinois, Urbana

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1995年 / 14卷 / 01期

基金：

美国国家科学基金会;

关键词：

D O I：

10.1109/43.363119

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we study the area minimization problem in floorplanning (also known as the floorplan sizing problem). For a given floorplan, the problem is to select a layout alternative for each subcircuit on a chip so as to minimize the chip area. Two area minimization methods for general floorplans are proposed. Both methods can be viewed as generalizations of the classical algorithm for slicing floorplans of Otten and Stockmeyer in the sense that they reduce naturally to their algorithm for slicing floorplans. Compared with the branch-and-bound algorithm of Wimer et at, which does not have a nontrivial performance bound, our methods are provably better than an exhaustive method for all the examples we examined.

引用

页码：123 / 132

页数：10

共 15 条

[11] OPTIMAL FLOORPLAN AREA OPTIMIZATION [J].

WANG, TC ;

WONG, DF .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1992, 11 (08) :992-1002

[12] OPTIMAL ASPECT RATIOS OF BUILDING-BLOCKS IN VLSI [J].

WIMER, S ;

KOREN, I ;

CEDERBAUM, I .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1989, 8 (02) :139-145

[13]

WONG DF, 1989, 26TH P ACM IEEE DES, P586

[14]

YEAP KH, 1993, EUR DES AUT C, P29

[15]

Zimmerman G., 1988, 25th ACM/IEEE Design Automation Conference. Proceedings 1988 (Cat. No.88CH2540-3), P60, DOI 10.1109/DAC.1988.14735

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