A 23-NS 4-MB CMOS SRAM WITH 0.2-MU A STANDBY CURRENT

被引:13
作者
SASAKI, K [1 ]
ISHIBASHI, K [1 ]
SHIMOHIGASHI, K [1 ]
YAMANAKA, T [1 ]
MORIWAKI, N [1 ]
HONJO, S [1 ]
IKEDA, S [1 ]
KOIKE, A [1 ]
MEGURO, S [1 ]
MINATO, O [1 ]
机构
[1] HITACHI LTD,DIV SEMICOND,KODAIRA,TOKYO 187,JAPAN
关键词
D O I
10.1109/4.62127
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A 4-Mb CMOS SRAM having 0.2-μA standby current at a supply voltage of 3 V has been developed. Current-mirror/PMOS cross-coupled cascade sense-amplifier circuits have achieved the fast address access time of 23 ns. A new noise-immune data-latch circuit has attained power reduction characteristics at a low operating cycle time without access delay. A 0.5-μm CMOS, four-level poly, and two-level metal technology with a polysilicon PMOS load memory cell has realized a small cell area of 17 μm2 and the very small standby current. A quadruple-array word-decoder architecture has enabled a small chip area of 122 mm2. © 1990 IEEE
引用
收藏
页码:1075 / 1081
页数:7
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