A NETWORK FLOW APPROACH TO THE RECONFIGURATION OF VLSI ARRAYS

被引：5

作者：

CODENOTTI, B ^{[1
]}

TAMASSIA, R ^{[1
]}

机构：

[1] BROWN UNIV,DEPT COMP SCI,PROVIDENCE,RI 02912

来源：

IEEE TRANSACTIONS ON COMPUTERS | 1991年 / 40卷 / 01期

关键词：

FAULT-TOLERANT SYSTEMS; NETWORK FLOW; SYSTOLIC ARRAYS; VLSI; WAFER SCALE INTEGRATION; WIRE LENGTH;

D O I：

10.1109/12.67329

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present a new technique for reconfiguring a two-dimensional VLSI array with faulty cells and compare it to existing ones. Using a network flow model of the problem, we provide an algorithm for connecting the functional cells of the array so that they simulate a fault-free array of smaller size. The interconnection wires are routed inside horizontal and vertical channels according to the Manhattan model. Experimental results indicate that our algorithm has a good performance in practice.

引用

页码：118 / 121

页数：4

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