POLYOXIDE THINNING LIMITATION AND SUPERIOR ONO INTERPOLY DIELECTRIC FOR NONVOLATILE MEMORY DEVICES

被引：22

作者：

MORI, S ^{[1
]}

ARAI, N ^{[1
]}

KANEKO, Y ^{[1
]}

YOSHIKAWA, K ^{[1
]}

机构：

[1] TOSHIBA MICROELECTR CORP,SAIWAI KU,KAWASAKI 210,JAPAN

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1991年 / 38卷 / 02期

关键词：

D O I：

10.1109/16.69905

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Results obtained from a study on thin interpoly dielectrics, especially for nonvolatile memories with stacked-gate structures. are presented. First, the key factors which dominate the leakage current in polyoxide are reviewed, and intrinsic limitations in thinner polyoxide for device applications are investigated considering defect densities and edge leakage current. Second, the ONO (Oxide/Nitride/Oxide) structure which overcomes polyoxide-thinning limitations is described. This stacked film reveals superior electric-field strength due to the inherent electron-trapping-assisted process. UV erase characteristics for EPROM cells with ONO structure are discussed. The slower erasing speed for EPROM cells with ONO interpoly dielectric is due to the decrease in photocurrent flow from a floating gate to a control gate.

引用

页码：270 / 277

页数：8

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