AN APPROPRIATE DEVICE FIGURE OF MERIT FOR BIPOLAR CML

被引：8

作者：

GREENEICH, EW

机构：

[1] Center for Solid State Electronics Research, Arizona State University, Tempe, AZ

来源：

IEEE ELECTRON DEVICE LETTERS | 1991年 / 12卷 / 01期

关键词：

D O I：

10.1109/55.75684

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The effects of base resistance, base transit time, and junction capacitances play a key role in the propagation delay of high-speed bipolar logic gates. A simple device figure of merit for transistors used in CML circuits is developed which is based upon minimum propagation delay. This delay is derived from the large-signal 3-dB cutoff frequency of the CML gate. Results are shown to be applicable for a wide range of device and circuit parameters.

引用

页码：18 / 20

页数：3

共 6 条

[1] METHOD OF ESTIMATING DELAY IN SWITCHING CIRCUITS + FIGURE OF MERIT OF SWITCHING TRANSISTOR [J].