ACCURATE ANALYTICAL DELAY EXPRESSIONS FOR ECL AND CML CIRCUITS AND THEIR APPLICATIONS TO OPTIMIZING HIGH-SPEED BIPOLAR CIRCUITS

A linearity study of the propagation delay of bipolar circuits has been carried out using a SPICE program. It is found that the behavior of the propagation delay is quite linear and therefore analytical propagation delay expressions for ECL and CML circuits are derived using a sensitivity analysis. The validity of these expressions is critically checked via SPICE simulations and experimental data published in the literature and agreement is obtained to 5%. The propagation delay expression for CML circuits is published for the first time in the literature. These expressions indicate that there is an optimum value of load resistance for logic Circulans in order to achieve a minimum propagation delay. For present technology, logic circuits for silicon transistors can operate at the current density of maximum fT , and logic circuits for Al GaAs/GaAs HBT should operate at a current density lower than that of maximum fT Therefore, the paper points out that it is important to increase the collector current density of maximum fT for silicon bipolar circuits, or to decrease the base resistance RB and the forward transit time Tf for HBT circuits in order to increase the circuit speed. 0018-9200/90/0400-0572$01.00 © 1990 IEEE