AN 8-NS 256K ECL SRAM WITH CMOS MEMORY ARRAY AND BATTERY BACKUP CAPABILITY

被引:10
作者
VANTRAN, H
SCOTT, DB
FUNG, PK
HAVEMANN, RH
EKLUND, RH
HAM, TE
HAKEN, RA
SHAH, AH
机构
[1] Texas Instruments Inc, Dallas, TX,, USA
关键词
DATA STORAGE; SEMICONDUCTOR -- Storage Devices - LOGIC CIRCUITS; EMITTER COUPLED - SEMICONDUCTOR DEVICES; MOS;
D O I
10.1109/4.5922
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The authors describe the first high-performance, high-density ECL SRAM (emitter-coupled-logic static random-access memory) compatible with battery backup techniques. The 256K device has a measured access time of 8 ns. Fabricated in a 0.8-μm BiCMOS process, the chip uses 117-μm2, full-CMOS, six-transistor memory cells and measures 6.5 × 8.15 mm2. The design methodology described here illustrates the extent to which bipolar devices can be integrated into the periphery of a CMOS memory array. This integration was achieved through the use of a novel sensing scheme which provided three stages of bipolar differential sensing, with the first stage of sensing taking place directly on the bit lines.
引用
收藏
页码:1041 / 1047
页数:7
相关论文
共 7 条
[1]  
CHAPMAN RA, 1987 IEDM, P362
[2]  
FUKUSHI I, 1988 ISSCC, P134
[3]  
HAVEMANN RH, 1987 IEDM, P841
[4]  
KERTIS RA, 1988 ISSCC, P186
[5]  
TAMBA N, 1988 ISSCC, P184
[6]   TITANIUM NITRIDE LOCAL INTERCONNECT TECHNOLOGY FOR VLSI [J].
TANG, TE ;
WEI, CC ;
HAKEN, RA ;
HOLLOWAY, TC ;
HITE, LR ;
BLAKE, TGW .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1987, 34 (03) :682-688
[7]  
YASHIMOTO M, 1983 ISSCC, P58