MOTION ESTIMATION ARCHITECTURE FOR VIDEO COMPRESSION

In this paper, we propose a VLSI architecture which implements the full search block matching motion estimation algorithm in real-time. The architecture consists of a 2-D structure of basic cells (BC's) where each BC is capable of computing the mean absolute error. The interblock dependency is exploited and hence the architecture can meet the real time requirement in various applications. Most importantly, the architecture is simple, modular and cascadable. This makes possible VLSI implementation as a codec.