A QUICK INTELLIGENT PAGE-PROGRAMMING ARCHITECTURE AND A SHIELDED BITLINE SENSING METHOD FOR 3-V-ONLY NAND FLASH MEMORY

被引:46
作者
TANAKA, T [1 ]
TANAKA, Y [1 ]
NAKAMURA, H [1 ]
SAKUI, K [1 ]
OODAIRA, H [1 ]
SHIROTA, R [1 ]
OHUCHI, K [1 ]
MASUOKA, F [1 ]
HARA, H [1 ]
机构
[1] TOSHIBA CO LTD,TOSHIBA SEMICONDUCTOR SYST ENGN CTR,KAWASAKI,KANAGAWA 210,JAPAN
关键词
Bitline-bitline capacitive coupling noise - NAND flash memories - Page programming architecture - Quick intelligent verify circuit - Shielded bitline sensing method - Verify circuit;
D O I
10.1109/4.328638
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper describes a quick intelligent page-programming architecture with a newly introduced intelligent verify circuit for 3 V-only NAND flash memories. The new verify circuit, which is composed of only two transistors, results in a simple intelligent program algorithm for 3 V-only operation and a reduction of the program time to 56%. This paper also describes a shielded bitline sensing method to reduce a bitline-bitline capacitive coupling noise from 700 mV to 35 mV. The large 700 mV noise without the shielded bitline architecture is mainly caused by the NAND-type cell array structure, A 3 V-only experimental NAND flash memory, developed in a 0.7-mu m NAND flash memory process technology, demonstrates that the programmed threshold voltages are controlled between 0.4 V and 1.8 V by the new verify circuit. The shielded bitline sensing method realizes a 2.5-mu s random access time with a 2.7-V power supply. The page-programming is completed after the 40-mu s program and 2.8-mu s verify read cycle is iterated 4 times. The block-erasing time is 10 ms.
引用
收藏
页码:1366 / 1373
页数:8
相关论文
共 6 条
  • [1] Aritome S., 1990, International Electron Devices Meeting 1990. Technical Digest (Cat. No.90CH2865-4), P111, DOI 10.1109/IEDM.1990.237214
  • [2] KIRISAWA R, 1990, JUN S VLSI TECHN PAP, P129
  • [3] Masuoka F., 1987, IEDM, P552
  • [4] A 4-MB NAND EEPROM WITH TIGHT PROGRAMMED VT DISTRIBUTION
    MOMODOMI, M
    TANAKA, T
    IWATA, Y
    TANAKA, Y
    OODAIRA, H
    ITOH, Y
    SHIROTA, R
    OHUCHI, K
    MASUOKA, F
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1991, 26 (04) : 492 - 496
  • [5] Shirota R., 1990, International Electron Devices Meeting 1990. Technical Digest (Cat. No.90CH2865-4), P103, DOI 10.1109/IEDM.1990.237216
  • [6] TANAKA T, 1992, JUN S VLSI CIRC, P20