REPROGRAMMABLE GATE ARRAYS FOR HARDWARE ACCELERATED IC DESIGN VERIFICATION

被引：1

作者：

DICKSON, JA ^{[1
]}

LIU, B ^{[1
]}

PTAK, AW ^{[1
]}

MCLEOD, RD ^{[1
]}

机构：

[1] UNIV MANITOBA,DEPT ELECT ENGN,VLSI RES LAB,WINNIPEG R3T 2N2,MANITOBA,CANADA

来源：

MICROPROCESSORS AND MICROSYSTEMS | 1990年 / 14卷 / 05期

基金：

加拿大自然科学与工程研究理事会;

关键词：

hardware emulation; IC design ASICs; microsystems; test LCAs;

D O I：

10.1016/0141-9331(90)90121-B

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The paper discusses the development of a hardware accelerator environment for ASIC design verification. A reprogrammable gate array serves as a breadboard for the ASIC design. Design entry is accepted in schematic or VHDL description form. An IC test instrument is used to program the gate array and run realtime functional tests on the ASIC design. It is anticipated that significant reductions in the ASIC development cycle can be achieved with this system, as well as allowing for more rapid design space exploration. Hardware accelerated logic and fault simulation is also accommodated when the reprogrammable gate array is configured as either the faulty or fault-free logic block of interest. © 1990.

引用

页码：291 / 296

页数：6