LOGIC FAULT MODEL FOR CROSSTALK INTERFERENCES IN DIGITAL CIRCUITS

被引:13
作者
ANGLADA, R
RUBIO, A
机构
关键词
D O I
10.1080/00207218908921096
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
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页码:423 / 425
页数:3
相关论文
共 4 条
[1]  
ABRAHAM JA, 1987, 1987 P NAT ADV STUD
[2]   AN APPROACH TO CROSSTALK EFFECT ANALYSIS AND AVOIDANCE TECHNIQUES IN DIGITAL CMOS VLSI CIRCUITS [J].
ANGLADA, R ;
RUBIO, A .
INTERNATIONAL JOURNAL OF ELECTRONICS, 1988, 65 (01) :9-17
[3]  
Maly W., 1987, 24th ACM/IEEE Design Automation Conference Proceedings 1987, P173, DOI 10.1145/37888.37914
[4]   ANALYSIS AND MODELING OF MULTILEVEL PARALLEL AND CROSSING INTERCONNECTION LINES [J].
TRIPATHI, VK ;
BUCOLO, RJ .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1987, 34 (03) :650-658