A SYSTEMATIC-APPROACH FOR DESIGN OF DIGIT-SERIAL SIGNAL-PROCESSING ARCHITECTURES

This paper presents a systematic unfolding transformation technique to transform bit-serial architectures into equivalent digit-serial ones. The novel feature of the unfolding technique lies in the generation of functionally correct control circuits in the digit-serial architectures. Bit-serial systems process one bit of a word or sample in a clock cycle. For some applications bit-serial architectures may be too slow, and bit-parallel architectures may be faster than necessary and may require too much hardware. The desired sample rate in these applications can be achieved using the digit-serial approach, where multiple bits of a sample are processed in a single clock cycle. The number of bits processed in one clock cycle in the digit-serial systems is referred to as the digit size; the digit size can be any arbitrary integer (the digit size was restricted to be a divisor of wordlength in the past ad hoc designs). We present digit-serial implementation of two's complement adders and multipliers. Least-significant-bit (Isb)-first bit-serial implementation of two's complement division, square-root, and compare-select operations are presented, and the corresponding digit-serial architectures for these operations are obtained using the unfolding algorithm. Unfolding of multiple-rate operations (such as interpolators and decimators) is also addressed.